One of the major problems facing semiconductor technology in its evolution toward submicron devices is that of dopant redistribution during dopant activation and annealing of ion implant junctions. Annealing of ion implanted damage has been the focus of considerable attention in recent years. The usually simple low cost furnace annealing of implantation damage has been found to be unacceptable for very large scale integrated applications because of substantial dopant redistribution. Stringent requirements of very large scale integrated circuits (VLSI) have made low temperature processing not only attractive but essential. High temperature processing makes tight dimensional control difficult and can even result in undesirable wafer warpage. In metal oxide semiconductor (MOS) circuits any lateral diffusion of implanted species from the source and drain can affect the channel length and also alter the channel doping. This can change the terminal characteristics of the devices considerably. Further, shallow implants are also needed for other devices such as shannon diodes, solar cells, etc. Conventional simple furnace annealing requires temperature as high as 1100.degree. C. to completely anneal ion implantation damage. Back side gettering using phosphorous has been successful in reducing these anneal temperatures from 1100.degree. C. to 950.degree. C. but this temperature range is still too high for the low temperature (i.e. temperatures less than 800.degree. C.) processing required in VLSI. Hence considerable effort in recent years has gone into the development of processes that anneal out implantation damage and result in dopant activation without the attendant phenomenon of dopant redistribution.
Ion implantation has become a powerful VLSI tool for the formation of heavily doped shallow junctions. However ion implantation is generally followed by greater than 850.degree. thermal anneal to remove the implantation damage and activate the dopants. Such high temperature anneal is not desirable and may be unacceptable for very shallow junctions (.ltoreq.0.1 .mu.m). In addition implantation of phosphorous and arsenic at high dose levels severely damages the crystal lattice and subsequently is difficult to anneal even at high temperatures (900.degree. C.). This tends to make the implanted junctions more leaky resulting in lower breakdown voltages. Therefore it is necessary to develop methods for completely annealing implantation damage preferably at low temperatures.
Consequently interest has moved to alternative techniques for annealing of ion implantation damage. Local annealing techniques employing laser beams or electron beams have proved effective in annealing out ion implantation damage. However it is recognized that the local melting and rapid solidification produced by these beam approaches usually leaves behind residual defects that are electrically active and may require furnace anneals with temperatures in excess of 600.degree. C. for their removal. Two other alternative techniques rapid thermal annealing (RTA) using incoherent light sources and strip heater annealing are also being used. For these two approaches the surface temperature of the silicon reaches 1000.degree. C. to 1200.degree. C. and hence they are not low temperature processes. In addition the heating and cooling rates involved are fast, of the order of seconds, and can induce stresses in silicon substrates.
These processes then can generally be classified into two broad categories: localized beam annealing which includes laser and electron beam annealing and rapid thermal annealing (RTA) which herein will be taken to include processes employing pulsed incoherent lamp sources or graphite strip heating. From the point of economy of time, localized beam annealing fares the best with anneal times of the order of seconds. The beam, laser or electron, is directed on a very small region at the surface rapidly bringing the silicon temperature up to a point where epitaxial regrowth can result. However the rapid localized heating and melting and cooling and solidification involved can result in imperfections in the lattice and can give rise to electrically active defects.
Rapid thermal anneals employing pulsed incoherent light sources for annealing ion implantation damage typically use pulse durations of the order of a few hundred microseconds with incident energies in a range of 20 to 30 joules/cm.sup.2. This approach can be used for the uniform annealing and dopant activation of large areas. Rapid thermal anneals using graphite strip heaters are equally effective. However, it has been shown that RTA at least for the case of graphite strip heaters produces annealed implanted layers that degrade under simulated subsequent low temperature processing. Both RTA approaches uniformly heat the damaged silicon layer. However, both bring the temperature of the whole silicon surface to the 1000.degree. to 1200.degree. C. range and consequently neither is a true low temperature process.
Hydrogen is generally believed to bond chemically to any dangling bonds in the silicon and in the energy band picture to move localized states in the band gap to the band edges. Successful demonstration of the reduction of bulk recombination centers in ribbon silicon using hydrogen ions as a passivant has been shown by Seager. Laser beam damage silicon exposed to a hydrogen plasma for four hours experienced a total passivation of residual point defects. Further, hydrogen is believed to be responsible for the low surface state density seen in MOS capacitor structures after a low temperature post metalization hydrogen anneal.